1. Field of the Invention
This invention relates to a semiconductor integrated circuit, specifically to a semiconductor integrated circuit using a WLP (Wafer Level Package) or a CSP (Chip Size Package).
2. Description of the Related Art
In recent years, the wafer level package (hereafter referred to as WLP) and the chip size package (hereafter referred to as CSP) have come into widespread use. The WLP and the CSP are packages intended for high density mounting, and have a size comparable to an LSI die packaged in it.
The WLP and the CSP are manufactured at a semiconductor fab, and is shipped to a customer after a pre-shipment test. The customer manufactures his products by mounting various kinds of electronic parts including the WLP or the CSP onto a circuit board using electronic parts mounting apparatus such as a chipmounter at his production plant. Related technologies are disclosed in Japanese Patent Application Publication Nos. 2000-188305 and 2005-72554, for example.
The WLP and the CSP are more susceptible to mechanical damage in handling or in mounting onto the circuit board compared with a resin mold package. Potential defects resulting from the damage are chipping or cracking of the LSI die, separation of a resin layer covering a surface of the LSI die and the like, which are prone to be caused in a periphery of the die.
In the production process at the customer, it is required for the purpose of helping failure analysis and improvement of the process that a location of the semiconductor die in which the defect is caused due to the stress applied to the WLP or the CSP when the WLP of the CSP is mounted onto the circuit board is electrically identified.
This invention is directed to offering a semiconductor integrated circuit provided with a function to detect the defect such as the chipping of the LSI die or the separation of the resin layer, specifically a function to electrically identify the location of the defect.